1. Technical Field
The present disclosure relates to a technique of driving a display device and, more particularly, to a source driver, a common voltage driver, and a method of driving a display device using a time division driving method.
2. Discussion of Related Art
Thin film transistor liquid crystal displays (hereinafter, referred to as TFT-LCDs) are representative flat panel display devices, and are widely used in TVs, monitors, cellular phones, and the like.
FIG. 1 is a block diagram of a conventional display device 1. Referring to FIG. 1, the conventional display device 1 includes a display panel 10, a source driver 100, and a common voltage driver 200. The display panel 10 includes a plurality of source lines S1 through Sm and a common voltage line, and displays an image signal in response to a common voltage VCOM applied to the common voltage line and an analog voltage corresponding to a digital image signal supplied to the source lines S1 through Sm.
FIG. 2 is a structure diagram of the source driver 100 that is driven using a time division driving method. Referring to FIG. 2, the source driver 100 includes a controller 110, a data selection circuit 120, a polarity control circuit 130, a latch circuit 140, a digital-to-analog converter (DAC) 150, an output buffer 160, and a plurality of switches SW1 through SWm.
The controller 110 generates a plurality of channel selection signals CSEL1 through CSELm, a polarity control signal PCS, and a latching signal LS in response to a clock signal CLK. The data selection circuit 120 receives a plurality of digital image data VD1 through VDm, selects one of the digital image data VD1 through VDm in response to the channel selection signals CSEL1 through CSELm from the controller 110, and outputs the selected image data. Each of the digital image data VD1 through VDm may include n bits (where n and m are natural numbers).
The polarity control circuit 130 selectively inverts output data of the data selection circuit 120 in response to the polarity control signal PCS and outputs the result of the selective inversion. The reason the inversion of the output data of the data selection circuit 120 is performed, as is generally known, is to prevent degradation of the liquid crystal. The latch circuit 140 receives and stores output data of the polarity control circuit 130, and outputs the output data of the polarity control circuit 130 to the DAC 150 in response to the latching signal LS.
The DAC 150 receives a plurality of analog voltages VG[2n:1] that are generated on the basis of the number of bits of the digital image data, and outputs an analog voltage corresponding to output data of the latch, circuit 140 from among the analog voltages VG[2n:1].
For example, when the digital image data includes n bits, the number of analog voltages VG[2n:1] is 2n and the DAC 150 outputs an analog voltage corresponding to the output data of the latch circuit 140 from among the 2n analog voltages VG[2n:1]. The output buffer 160 receives a first power supply voltage AVDD, and buffers and outputs the analog voltage outputted from the DAC 150. The output buffer 160 improves the current driving ability of the source driver 100.
The switches SW1 through SWm output the analog voltage buffered by the output buffer 160 to one of the source lines S1 through Sm in response to the channel selection signals CSEL1 through CSELm.
FIG. 3 is a structure diagram of the common voltage driver 200. Referring to FIG. 3, the common voltage driver 200 includes an output terminal VCOM, a first amplifier 210, a second amplifier 220, a first switch SW1, and a second switch SW2.
The first amplifier 210 receives the first power supply voltage AVDD, and amplifies a first input voltage Vin1 to output a first voltage VCOMH. The second amplifier 220 receives a second power supply voltage VCL, and amplifies a second input voltage Vin2 to output a second voltage VCOML. The first switch SW1 is connected between an output terminal of the first amplifier 210 and the output terminal VCOM, and is switched on to supply the first voltage VCOMH to the output terminal VCOM in response to a first voltage control signal VCS1.
The second switch SW2 is connected between an output terminal of the second amplifier 220 and the output terminal VCOM, and is switched on to supply the second voltage VCOML, to the output terminal. VCOM in response to a second voltage control signal VCS2.
FIG. 4 is a timing diagram representing time-division driving operations of the source driver 100 and the common voltage driver 200 shown in FIG. 2 and FIG. 3, respectively. Referring to FIGS. 2 through 4, the channel selection signals CSEL1 through CSELm, which have predetermined activation sections, for example, high levels are applied to the data selection circuit 120 and the switches SW1 through SWm.
The data selection circuit 120 selects and outputs one of the digital image data VD1 through VDm in response to the channel selection signals CSEL1 through CSELm, and the switches SW1 through SWm output the analog voltage buttered by the output buffer 160 to a corresponding source line out of the source lines S1 through Sm in response to the channel selection signals CSEL1 through CSELm.
The polarity control signal PCS is applied to the polarity control circuit 130. The polarity control circuit 130 inverts a polarity of the output data of the data selection circuit 120 every horizontal scan period 1H.
The latching signal LS has as many activation sections as the number of channel selection signals CSEL1 through CSELm and is activated at the points in time when the channel selection signals are activated. The latching circuit 140 outputs the stored digital image data at the points in time when, the latching signal LS is activated.
The first voltage control signal VCS1 is in phase with the polarity control signal PCS, and the second voltage control signal VCS2 is in opposite phase with the first voltage control signal VCS1. When the first voltage control signal VCS1 is activated, the voltage level of the output terminal VCOM, of the common voltage driver 200 becomes the first voltage VCOMH. When the second voltage control signal VCS2 is activated, the voltage level of the output terminal VCOM becomes the second voltage VCOML.
FIG. 5 is a block diagram of a boosting circuit of a general display device, and FIG. 6 illustrates a load model of a general display panel.
Referring to FIG. 5, the boosting circuit receives a reference voltage VDD and outputs the first power supply voltage AVDD, which is obtained by amplifying the reference voltage VDD a times, and the second power supply voltage VCL, which is obtained by amplifying the reference voltage VDD-β times. Here, α is an integer equal to or greater than 2, and β is an integer equal to or greater than 1. Referring to FIG. 6, Cs denotes an equivalent capacitor viewed from a source line, and Ccom denotes an equivalent capacitor viewed from a ground line to which the output terminal of the common voltage driver 200 may be connected.
A maximum average current consumed for one horizontal scan period 1H(1T) upon the aforementioned driving operations of the source driver 100 and the common voltage driver 200 using a general time division driving method will now be described. Referring to FIG. 4, when a polarity of the common voltage VCOM is opposite to that of an analog voltage supplied to a source line, a maximum average current is consumed in the display panel 10.
An average current Iavdd for the first power supply voltage AVDD supplied to the output buffer 160 of the source driver 100 is calculated using Equation 1;
                    Iavdd        =                              Cs            ⁡                          (                              VCOMH                -                VCOML                +                VH                -                VL                            )                                            2            ⁢            T                                              (        1        )            
An average current Ivcomh for the first power supply voltage AVDD supplied to the first amplifier 210 of the common voltage driver 200 is calculated using Equation 2:
                    Ivcomh        =                                                                                                  Cs                    ⁢                                          (                                              VCOMH                        -                        VCOML                        +                        VH                        -                        VL                                            )                                                        +                                                                                                      Ccom                  ⁡                                      (                                          VCOMH                      -                      VCOML                                        )                                                                                            2            ⁢            T                                              (        2        )            
An average current Ivcom1 for the second power supply voltage VCL supplied to the second amplifier 220 of the common voltage driver 200 is calculated using Equation 3:
                    Ivcoml        =                                                                                                  Cs                    ⁡                                          (                                              VCOMH                        -                        VCOML                        +                        VH                        -                        VL                                            )                                                        +                                                                                                      Ccom                  ⁡                                      (                                          VCOMH                      -                      VCOML                                        )                                                                                            2            ⁢            T                                              (        3        )            
A total average current Itot for the reference voltage VDD of the source driver 100 and the common voltage driver 200, being an average of the average currents of Equations 1 and 3, is calculated using Equation 4:
                    Itot        =                                                                                                                        (                                              2                                                  α                          +                          β                                                                    )                                        ⁢                                          Cs                      ⁡                                              (                                                  VCOMH                          -                          VCOML                          +                          VH                          -                          VL                                                )                                                                              +                                                                                                                          (                                          α                      +                      β                                        )                                    ⁢                                      Ccom                    ⁡                                          (                                              VCOMH                        -                        VCOML                                            )                                                                                                                2            ⁢            T                                              (        4        )            
As shown in Equations 1 through 4, when the source driver 100 and the common voltage driver 200 are driven using a generally known time division driving method, a large amount of current is consumed in the display device 1.